DRAM memory is typically made of one transistor and one capacitor cell (1T1C). While the transistor functions as pass, the capacitor is used for charge storage. The capacitor can be either a trench configuration or a stacked capacitor. A certain novel class of DRAM memories can be comprised of only one transistor, without the need for a capacitor, and hence is referred to as capacitorless DRAM, 1T, or 1T-RAM. Such memory types are usually based on Semiconductor-on-Insulator (SeOI)-like substrates, where the transistor, through its floating body characteristics, acts as both control transitory and charge storage device. Examples of such type are the “Floating Body Cell” (FBC), or the “zero-capacitor RAM” (zRAM) though other variations exist.
A typical 1T memory is illustrated in FIG. 1.
The SeOI substrate comprises from its base to its top a base wafer 10, an insulating layer 20 and a top semiconductor layer 30, also called a “useful layer.”
The memory device is made of transistors made on the semiconductor useful layer 30. The source S and drain D are made in the useful layer 30, whereas the gate G is deposited on an insulating layer on the useful layer 30.
For a certain class of 1T memory that requires back-bias, such as the FBC, an electrode E is also installed on the rear side of the substrate, i.e., on the base wafer 10.
During operation of the 1T memory, charges (holes) are injected from the channel near the drain region via impact ionization into the body of the transistor. The presence of these positive charges shifts the Vt of the transistor lower and changes the current-voltage characteristics. This shift is used to detect or “read” the state of the cell, being either “1” or “0.”
1T memory being a volatile memory, a periodic refresh is carried out in order to restore charge, and hence programming state, to the transistor. Charge is mainly lost through various leakage mechanisms, and the rate of charge loss determines the retention time of the memory cell. If such time is short, extensive refreshing is needed resulting in high power consumption and poor yield. Therefore, it is highly desirable to extend the retention time of the cell, i.e., charge retention in the transistor as much as practical. To that end, a rear electrode E can be used to apply a negative voltage in order to keep the charges in the transistor body as long as possible, e.g., near a back interface in the 1T design.
However, the installation of the rear electrode E requires additional processing and complex circuits that makes it expensive.
There is thus a need for a SeOI-like substrate that allows increasing the retention time of the 1T memories, at a lower cost.